The invention relates to integrated circuit devices, and more particularly to the estimation of layout sensitivity in a transistor array.
It has long been known that semiconductor materials such as silicon and germanium exhibit the piezoelectric effect (mechanical stress-induced changes in electrical resistance). See for example C. S. Smith, “Piezoresistance effect in germanium and silicon”, Phys. Rev., vol. 94, pp. 42-49 (1954), incorporated by reference herein. It has also been observed that stress variations in a transistor array can produce variations in carrier mobility, which in turn leads to variations in threshold voltage in the transistors of the array. That problem, and a solution for it, are set out in U.S. patent application Ser. No. 11/291,294, entitled “Analysis of Stress Impact on Transistor Performance”, assigned to the assignee hereof.
Further study has shown, however, that beyond stress impact on electron and hole mobilities, layout also affects threshold voltage, suggesting some additional factor at work. Variations encountered have been far from trivial, with swings of over 20 mV being common. The art has not suggested any potential causes for such problems, nor has it presented solutions. Thus, it has remained for the present inventors to discover the cause of such variations and to devise solutions, all of which are set out below.